This invention relates to wideband code division multiple access (WCDMA) for a communication system and more particularly to space time block coded transmit antenna diversity for frame synchronization of WCDMA signals.
Present code division multiple access (CDMA) systems are characterized by simultaneous transmission of different data signals over a common channel by assigning each signal a unique code. This unique code is matched with a code of a selected receiver to determine the proper recipient of a data signal. These different data signals arrive at the receiver via multiple paths due to ground clutter and unpredictable signal reflection. Additive effects of these multiple data signals at the receiver may result in significant fading or variation in received signal strength. In general, this fading due to multiple data paths may be diminished by spreading the transmitted energy over a wide bandwidth. This wide bandwidth results in greatly reduced fading compared to narrow band transmission modes such as frequency division multiple access (FDMA) or time division multiple access (TDMA).
New standards are continually emerging for next generation wideband code division multiple access (WCDMA) communication systems as described in Provisional U.S. Patent Application No. 60/082,671, filed Apr. 22, 1998, and incorporated herein by reference. These WCDMA systems are coherent communications systems with pilot symbol assisted channel estimation schemes. These pilot symbols are transmitted as quadrature phase shift keyed (QPSK) known data in predetermined time frames to any receivers within range. The frames may propagate in a discontinuous transmission (DTX) mode. For voice traffic, transmission of user data occurs when the user speaks, but no data symbol transmission occurs when the user is silent. Similarly for packet data, the user data may be transmitted only when packets are ready to be sent. The frames are subdivided into sixteen equal time slots of 0.625 milliseconds each. Each time slot is further subdivided into equal symbol times. At a data rate of 32 KSPS, for example, each time slot includes twenty symbol times. Each frame includes pilot symbols as well as other control symbols such as transmit power control (TPC) symbols and rate information (RI) symbols. These control symbols include multiple bits otherwise known as chips to distinguish them from data bits. The chip transmission time (TC), therefore, is equal to the symbol time rate (T) divided by the number of chips in the symbol (N).
Previous studies have shown that multiple transmit antennas may improve reception by increasing transmit diversity for narrow band communication systems. In their paper New Detection Schemes for Transmit Diversity with no Channel Estimation, Tarokh et al. describe such a transmit diversity scheme for a TDMA system The same concept is described in A Simple Transmitter Diversity Technique for Wireless Communications by Alamouti. Tarokh et al and Alamouti, however, fail to teach such a transmit diversity scheme for a WCDMA communication system.
Other studies have investigated open loop transmit diversity schemes such as orthogonal transmit diversity (OTD) and time switched time diversity (TSTD) for WCDMA systems. Both OTD and TSTD systems have similar performance. Both use multiple transmit antennas to provide some diversity against fading, particularly at low Doppler rates and when there are insufficient paths for the rake receiver. Both OTD and TSTD systems, however, fail to exploit the extra path diversity that is possible for open loop systems. For example, the OTD encoder circuit of FIG. 5 receives symbols S1 and S2 on lead 500 and produces output signals on leads 504 and 506 for transmission by first and second antennas, respectively. These transmitted signals are received by a despreader input circuit (not shown). The despreader circuit sums received chip signals over a respective symbol time to produce first and second output signals Rj1 and Rj2 on leads 620 and 622 as in equations [1-2], respective                               R          j          1                =                                            ∑                              i                =                0                                            N                -                1                                      ⁢                                          r                j                            ⁡                              (                                  i                  +                                      τ                    j                                                  )                                              =                                                    α                j                1                            ⁢                              S                1                                      +                                          α                j                2                            ⁢                              S                2                                                                        [        1        ]                                          R          j          2                =                                            ∑                              i                =                N                                                              2                  ⁢                  N                                -                1                                      ⁢                                          r                j                            ⁡                              (                                  i                  +                                      τ                    j                                                  )                                              =                                                    α                j                1                            ⁢                              S                1                                      -                                          α                j                2                            ⁢                              S                2                                                                        [        2        ]            
The OTD phase correction circuit of FIG. 6 receives the output signals Rj1 and Rj2 corresponding to the jth of L multiple signal paths. The phase correction circuit produces soft outputs or signal estimates {tilde over (S)}1 and {tilde over (S)}2 for symbols S1 and S2 at leads 616 and 618 as shown in equations [3-4], respectively.                                           S            ~                    1                =                                            ∑                              j                =                1                            L                        ⁢                                          (                                                      R                    j                    1                                    +                                      R                    j                    2                                                  )                            ⁢                              α                j                                  1                  *                                                              =                                    ∑                              j                =                1                            L                        ⁢                          2              ⁢                                                "LeftBracketingBar"                                      α                    j                    1                                    "RightBracketingBar"                                2                            ⁢                              S                1                                                                        [        3        ]                                                      S            ~                    2                =                                            ∑                              j                =                1                            L                        ⁢                                          (                                                      R                    j                    1                                    -                                      R                    j                    2                                                  )                            ⁢                              α                j                                  2                  *                                                              =                                    ∑                              j                =                1                            L                        ⁢                          2              ⁢                                                "LeftBracketingBar"                                      α                    j                    2                                    "RightBracketingBar"                                2                            ⁢                              S                2                                                                        [        4        ]            
Equations [3-4] show that the OTD method provides a single channel estimate xcex1 for each path j. A similar analysis for the TSTD system yields the same result. The OTD and TSTD methods, therefore, are limited to a path diversity of L. This path diversity limitation fails to exploit the extra path diversity that is possible for open loop systems as will be explained in detail.
These problems are resolved by a circuit is designed with a correction circuit coupled to receive a first estimate signal, a second estimate signal, and a plurality of input signals from an external source along plural signal paths. The plurality of input signals includes a first and a second input signal. The correction circuit produces a first symbol estimate in response to the first and second estimate signals and the first and second input signals. The correction circuit produces a second symbol estimate in response to the first and second estimate signals and the first and second input signals. A combining circuit is coupled to receive a plurality of first symbol estimates including the first symbol estimate and a plurality of second symbol estimates including the second symbol estimate. The combining circuit produces a first symbol signal in response to the plurality of first symbol estimates and a second symbol signal in response to the plurality of second symbol estimates. A synchronization circuit is coupled to receive the first and second symbol signals and a first known symbol and a second known symbol. The synchronization circuit produces a synchronization signal in response to an approximate match between the first symbol signal and the first known symbol and between the second symbol signal and the second known symbol.
The present invention improves frame synchronization by providing at least 2L diversity over time and space. No additional transmit power or bandwidth is required. Power is balanced across multiple antennas.